A Low-power Cache System for High-performance Processors

In modern processors, a cache system becomes the main contributor of the total power consumption as it greatly improves the performance. Most of the power consumption is caused by its complex architecture, very frequent access and progressively increased size. This thesis presents three techniques in a cache system in order to reduce both power consumption and access latency. We also propose a novel recovery mechanism, which uses a special ‘cache’ to eliminate the performance degradation due to our proposed optimization. In Chapter 1, we first review the principle of cache and two popular cache architectures. Then, we analyzed the cache access time and energy. Based on these theoretical foundations and analysis, we survey the current mainstream techniques on high-speed and low-power cache designs. These techniques improve the performance or reduce the power consumption at many levels, such as device level, circuit level, and so on. By referring to and developing the previous techniques, we propose four approaches in next the chapters, considering both performance and power consumption of cache. In Chapter 2, we first propose a low-power Data Cache (D-Cache) design, called Adaptive Various-width Data Cache (AVDC), which exploits the value locality to reduce the static power consumption and dynamic power consumption of D-Cache. There is a common understanding such as many values in a processor rarely need the full-bit dynamic range supported by a cache. The narrow-width value occupies a large portion of the cache access and storage. From the view of this observation, AVDC exploits the popularity of narrow-width values to reduce the power consumption of D-Cache without performance degradation. The data storage unit in AVDC consists of three subarrays to store data with different widths. When the high sub-arrays are not used, the modified high-bit SRAM cells can be closed to save their dynamic and static power consumption. The main advantages of AVDC are: 1) Both the dynamic and static power consumption can be reduced. 2) Low power consumption is achieved by the modification of the data storage unit with less hardware modification. 3) We exploit the redundancy of narrow-width values instead of compressed values, thus cache access latency does not increase. Experimental results using SPEC 2000 benchmarks show that our proposed AVDC can reduce the power consumption, by 34.83% for dynamic power consumption and by 42.87% for static power consumption on average, compared with a traditional D-Cache. In Chapter 3, as the second technique, we present a new power-aware Instruction Fetch Unit (IFU) architecture, named Analysis Before Starting an Access (ABSA), which aims at maximizing the power efficiency of the low-power techniques on Instruction Cache (I-Cache) by eliminating the restrictions on those low-power techniques in the traditional IFU. To achieve this goal, ABSA